
//simulation files
//top
`include "../verilog/source/sim_tb_top.v"
`include "../verilog/source/glbl.v"
//test memc
`include "../verilog/source/ddr2_test/memc1_tb_top.v"
`include "../verilog/source/ddr2_test/mcb_traffic_gen.v"
`include "../verilog/source/ddr2_test/init_mem_pattern_ctr.v"
`include "../verilog/source/ddr2_test/write_data_path.v"
`include "../verilog/source/ddr2_test/afifo.v"
`include "../verilog/source/ddr2_test/cmd_gen.v"
`include "../verilog/source/ddr2_test/mcb_flow_control.v"
`include "../verilog/source/ddr2_test/read_data_path.v"
`include "../verilog/source/ddr2_test/tg_status.v"
`include "../verilog/source/ddr2_test/rd_data_gen.v"
`include "../verilog/source/ddr2_test/wr_data_gen.v"
`include "../verilog/source/ddr2_test/read_posted_fifo.v"
`include "../verilog/source/ddr2_test/cmd_prbs_gen.v"
`include "../verilog/source/ddr2_test/data_prbs_gen.v"
`include "../verilog/source/ddr2_test/sp6_data_gen.v"

//user define test
`include "../verilog/example/dram_access.v"

//model
//ddr2
//`include "../verilog/model/ddr2_model_parameters_c1.vh"
//`include "../verilog/model/ddr2_model_c1.v"                                

//memory controller
`include "../verilog/memc/fruc_memc.v"
`include "../verilog/memc/memc1_wrapper.v"
`include "../verilog/memc/mcb_raw_wrapper.v"
`include "../verilog/memc/memc1_infrastructure.v"
`include "../verilog/memc/mcb_soft_calibration_top.v"
`include "../verilog/memc/mcb_soft_calibration.v"
`include "../verilog/memc/iodrp_controller.v"
`include "../verilog/memc/iodrp_mcb_controller.v"
